An information processing apparatus has been known which includes a semiconductor memory removable therefrom and which operates using data containing a program stored in the semiconductor memory. A variety of mechanisms have been proposed to provide the security of the data stored in this semiconductor memory.
Japanese Patent Application Laid-Open No. 9-106690 (1997) discloses a technique for scrambling data outputted from a semiconductor memory by the use of key data to provide the security of the data.
Japanese Patent Application Laid-Open No. 2001-35171 or Japanese Patent Application Laid-Open No. 7-219852 (1995) discloses a technique of performing a type of encryption by means of a logic circuit (logic) on address data outputted to a semiconductor memory or data outputted from the semiconductor memory to provide the security of the data.
Japanese Patent Application Laid-Open No. 9-106690, however, discloses a security method using a scrambling scheme which is advantageous in high data transfer efficiency but is disadvantageous in generally low strength of security. Japanese Patent Application Laid-Open No. 2001-35171 or Japanese Patent Application Laid-Open No. 7-219852 employs a one-step logic operation by means of the logic circuit, which features fast processing but is disadvantageous in low confidentiality because it is easy to analyze the security method if what logic circuit is used is known. To improve the confidentiality, it is contemplated to use an encryption scheme such that an inexpensive processing circuit such as a single-chip microcomputer is inserted between the semiconductor memory and the information processing apparatus to process a cryptographic algorithm. The security method employing such an encryption scheme, however, is disadvantageous in low data transfer efficiency although having the advantage of its high strength of security.
The technology herein is intended for a semiconductor memory device removably mounted to an information processing apparatus. According to an exemplary illustrative non-limiting implementation, the semiconductor memory device comprises: a memory core section for storing therein data including a program to be protected, the memory core section including an address input section and a data output section; an input/output terminal section including command input terminals for receiving a command including an instruction code and address data from the information processing apparatus, and data output terminals for providing data read from the memory core section to the information processing apparatus; and a memory control means connected between the memory core section and the input/output terminal section, the memory control means including a command decryption means selectively operative to decrypt the command provided to the command input terminals or to output the command without processing, a scrambling means selectively operative to scramble the data read from the memory core section or to output the data without processing, a command judgment means for judging whether the command provided from the information processing apparatus is a first command specifying a transition to a first operating mode or a second command specifying a transition to a second operating mode, and an operating mode control means selecting the first operating mode for enabling a command decryption function of the command decryption means in response to a judgment made by the command judgment means that the command is the first command, and selecting the second operating mode for enabling a scrambling function of the scrambling means in response to a judgment made by the command judgment means that the command is the second command.
Preferably, the memory control means includes a descrambling means selectively operative to pass the command provided to the command input terminals without processing therethrough or to descramble the command, and the operating mode control means disables a descrambling function of the descrambling means when the first operating mode is selected.
Preferably, the operating mode control means enables the descrambling function of the descrambling means when the second operating mode is selected.
The exemplary illustrative non-limiting implementation has the plurality of operating modes different in security strength, and operates while changing between these operating modes to provide the semiconductor memory device with enhanced security strength and excellent read performance.
Preferably, the memory control means includes a register for setting a scrambling condition of the scrambling means, and the operating mode control means updates the contents of the register during an operation in the first operating mode.
Preferably, the semiconductor memory device is controlled by a command provided from the information processing apparatus so that a period of operation in the first operating mode is longer than a period of operation in the second operating mode.
The semiconductor memory device according to the exemplary illustrative non-limiting implementation initializes the condition of scrambling processing when in a mode in which encryption is used and security strength is high while operating mainly in a mode in which scrambling is used and security strength is low. This efficiently compensates for the strength of the security in the mode in which the security strength is low, to provide excellent read performance on average for all of the operating modes.
It is therefore an object of the exemplary illustrative non-limiting implementation to provide a semiconductor memory having a high-level security function and excellent read performance in consideration for a balance between the strength of security and data transfer efficiency.